On Wed, 1 Apr 2020 at 08:35, Paolo Bonzini <pbonzini@xxxxxxxxxx> wrote:
>
> On 01/04/20 02:19, Wanpeng Li wrote:
> > - /* No delay here, so we always clear the pending bit */
> > - val &= ~(1 << 12);
> > + /* Immediately clear Delivery Status in xAPIC mode */
> > + if (!apic_x2apic_mode(apic))
> > + val &= ~(1 << 12);
>
> This adds a conditional, and the old behavior was valid according to the
> SDM: "software should not assume the value returned by reading the ICR
> is the last written value".
We can queue patch 1/2 separately to catch the merge window. :)
Wanpeng
