On 03/02/2020 14.19, Christian Borntraeger wrote:
> From: Janosch Frank <frankja@xxxxxxxxxxxxx>
>
> Since KVM doesn't emulate any form of load control and load psw
> instructions anymore, we wouldn't get an interception if PSWs or CRs
> are changed in the guest. That means we can't inject IRQs right after
> the guest is enabled for them.
I had to read that twice to understand it. I'd suggest maybe rather
something like:
Since there is no interception for load control and load psw instruction
in the protected mode, we need a new way to get notified whether we have
to inject an IRQ right after the guest has just enabled the possibility
for receiving them.
> The new interception codes solve that problem by being a notification
maybe s/being/providing/
> for changes to IRQ enablement relevant bits in CRs 0, 6 and 14, as
> well a the machine check mask bit in the PSW.
>
> No special handling is needed for these interception codes, the KVM
> pre-run code will consult all necessary CRs and PSW bits and inject
> IRQs the guest is enabled for.
>
> Signed-off-by: Janosch Frank <frankja@xxxxxxxxxxxxx>
> ---
> arch/s390/include/asm/kvm_host.h | 2 ++
> arch/s390/kvm/intercept.c | 10 ++++++++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h
> index 841690d05080..d63ed05272ec 100644
> --- a/arch/s390/include/asm/kvm_host.h
> +++ b/arch/s390/include/asm/kvm_host.h
> @@ -215,6 +215,8 @@ struct kvm_s390_sie_block {
> #define ICPT_PARTEXEC 0x38
> #define ICPT_IOINST 0x40
> #define ICPT_KSS 0x5c
> +#define ICPT_PV_MCHKR 0x60
> +#define ICPT_PV_INT_EN 0x64
> __u8 icptcode; /* 0x0050 */
> __u8 icptstatus; /* 0x0051 */
> __u16 ihcpu; /* 0x0052 */
> diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c
> index a389fa85cca2..eaa2a21c3170 100644
> --- a/arch/s390/kvm/intercept.c
> +++ b/arch/s390/kvm/intercept.c
> @@ -480,6 +480,16 @@ int kvm_handle_sie_intercept(struct kvm_vcpu *vcpu)
> case ICPT_KSS:
> rc = kvm_s390_skey_check_enable(vcpu);
> break;
> + case ICPT_PV_MCHKR:
> + /* fallthrough */
> + case ICPT_PV_INT_EN:
> + /*
> + * PSW bit 13 or a CR (0, 6, 14) changed and we might
> + * now be able to deliver interrupts. The pre-run code
> + * will take care of this.
> + */
> + rc = 0;
> + break;
> default:
> return -EOPNOTSUPP;
> }
With "fallthrough" removed and the commit message improved:
Reviewed-by: Thomas Huth <thuth@xxxxxxxxxx>
