> From: Peter Xu [mailto:peterx@xxxxxxxxxx] > Sent: Wednesday, September 25, 2019 2:50 PM > > On Mon, Sep 23, 2019 at 08:24:54PM +0800, Lu Baolu wrote: > > +/* > > + * Check and return whether first level is used by default for > > + * DMA translation. > > + */ > > +static bool first_level_by_default(void) > > +{ > > + struct dmar_drhd_unit *drhd; > > + struct intel_iommu *iommu; > > + > > + rcu_read_lock(); > > + for_each_active_iommu(iommu, drhd) > > + if (!sm_supported(iommu) || > > + !ecap_flts(iommu->ecap) || > > + !cap_caching_mode(iommu->cap)) > > + return false; > > + rcu_read_unlock(); > > + > > + return true; > > +} > > "If no caching mode, then we will not use 1st level." > > Hmm, does the vIOMMU needs to support caching-mode if with the > solution you proposed here? Caching mode is only necessary for > shadowing AFAICT, and after all you're going to use full-nested, > then... then I would think it's not needed. And if so, with this > patch 1st level will be disabled. Sounds like a paradox... > > I'm thinking what would be the big picture for this to work now: For > the vIOMMU, instead of exposing the caching-mode, I'm thinking maybe > we should expose it with ecap.FLTS=1 while we can keep ecap.SLTS=0 > then it's natural that we can only use 1st level translation in the > guest for all the domains (and I assume such an ecap value should > never happen on real hardware, am I right?). > yes, that's also the picture in my mind. :-) Thanks Kevin
