On Tue, Jul 30, 2019 at 6:48 PM Paolo Bonzini <pbonzini@xxxxxxxxxx> wrote: > > On 30/07/19 14:45, Anup Patel wrote: > > Here's some text from RISC-V spec regarding SIP CSR: > > "software interrupt-pending (SSIP) bit in the sip register. A pending > > supervisor-level software interrupt can be cleared by writing 0 to the SSIP bit > > in sip. Supervisor-level software interrupts are disabled when the SSIE bit in > > the sie register is clear." > > > > Without RISC-V hypervisor extension, the SIP is essentially a restricted > > view of MIP CSR. Also as-per above, S-mode SW can only write 0 to SSIP > > bit in SIP CSR whereas it can only be set by M-mode SW or some HW > > mechanism (such as S-mode CLINT). > > But that's not what the spec says. It just says (just before the > sentence you quoted): > > A supervisor-level software interrupt is triggered on the current > hart by writing 1 to its supervisor software interrupt-pending (SSIP) > bit in the sip register. Unfortunately, this statement does not state who is allowed to write 1 in SIP.SSIP bit. I quoted MIP CSR documentation to highlight the fact that only M-mode SW can set SSIP bit. In fact, I had same understanding as you have regarding SSIP bit until we had MSIP issue in OpenSBI. (https://github.com/riscv/opensbi/issues/128) > > and it's not written anywhere that S-mode SW cannot write 1. In fact > that text is even under sip, not under mip, so IMO there's no doubt that > S-mode SW _can_ write 1, and the hypervisor must operate accordingly. Without hypervisor support, SIP CSR is nothing but a restricted view of MIP CSR thats why MIP CSR documentation applies here. I think this discussion deserves a Github issue on RISC-V ISA manual. If my interpretation is incorrect then it would be really strange that HART in S-mode SW can inject IPI to itself by writing 1 to SIP.SSIP bit. > > In fact I'm sure that if Windows were ever ported to RISC-V, it would be > very happy to use that feature. On x86, Intel even accelerated it > specifically for Microsoft. :) That would be indeed very strange usage. :) Regards, Anup
