On Tue, Jul 30, 2019 at 2:30 PM Paolo Bonzini <pbonzini@xxxxxxxxxx> wrote: > > On 29/07/19 13:57, Anup Patel wrote: > > This patch implements all required functions for programming > > the stage2 page table for each Guest/VM. > > > > At high-level, the flow of stage2 related functions is similar > > from KVM ARM/ARM64 implementation but the stage2 page table > > format is quite different for KVM RISC-V. > > FWIW I very much prefer KVM x86's recursive implementation of the MMU to > the hardcoding of pgd/pmd/pte. I am not asking you to rewrite it, but > I'll mention it because I noticed that you do not support 48-bit guest > physical addresses. Yes, I also prefer recursive page table programming. In fact, the first hypervisor we ported for RISC-V was Xvisor and over there have recursive page table programming for both stage1 and stage2. BTW, 48bit VA and guest physical address is already defined in latest RISC-V spec. It's just that there is not HW (or QEMU) implementation as of now for 4-level page table. I will certainly add this to our TODO list. Regards, Anup
