On Tue, Jan 15, 2019 at 12:06 PM Krish Sadhukhan <krish.sadhukhan@xxxxxxxxxx> wrote: > > > > On 01/15/2019 11:02 AM, Jim Mattson wrote: > > On Tue, Jan 15, 2019 at 10:30 AM Krish Sadhukhan > > <krish.sadhukhan@xxxxxxxxxx> wrote: > >> According to section "Checks on VMX Controls" in Intel SDM vol 3C, the > >> following checks performed for the VM-entry MSR-load address if the > >> the VM-entry MSR-load count field is non-zero: > >> > >> - The lower 4 bits of the VM-entry MSR-load address must be 0. > >> The address should not set any bits beyond the processor’s > >> physical-address width. > >> > >> - The address of the last byte in the VM-entry MSR-load area > >> should not set any bits beyond the processor’s physical-address > >> width. The address of this last byte is VM-entry MSR-load address > >> + (MSR count * 16) - 1. (The arithmetic used for the computation > >> uses more bits than the processor’s physical-address width.) > >> > >> If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits > >> in the range 63:32. > >> > >> Signed-off-by: Krish Sadhukhan <krish.sadhukhan@xxxxxxxxxx> > >> Reviewed-by: Mihai Carabas <mihai.carabas@xxxxxxxxxx> Reviewed-by: Jim Mattson <jmattson@xxxxxxxxxx>
