Re: [kvm-unit-test nVMX 2/2]: Check VM-entry MSR-load address on vmentry of L2 guests

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On Tue, Jan 15, 2019 at 10:30 AM Krish Sadhukhan
<krish.sadhukhan@xxxxxxxxxx> wrote:
>
> According to section "Checks on VMX Controls" in Intel SDM vol 3C, the
> following checks performed for the VM-entry MSR-load address if the
> the VM-entry MSR-load count field is non-zero:
>
>     - The lower 4 bits of the VM-entry MSR-load address must be 0.
>       The address should not set any bits beyond the processor’s
>       physical-address width.
>
>     - The address of the last byte in the VM-entry MSR-load area
>       should not set any bits beyond the processor’s physical-address
>       width. The address of this last byte is VM-entry MSR-load address
>       + (MSR count * 16) - 1. (The arithmetic used for the computation
>       uses more bits than the processor’s physical-address width.)
>
>       If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits
>       in the range 63:32.
>
> Signed-off-by: Krish Sadhukhan <krish.sadhukhan@xxxxxxxxxx>
> Reviewed-by: Mihai Carabas <mihai.carabas@xxxxxxxxxx>
> ---
>  x86/vmx_tests.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 68 insertions(+)
>
> diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c
> index 02cd868..e02fc30 100644
> --- a/x86/vmx_tests.c
> +++ b/x86/vmx_tests.c
> @@ -4827,12 +4827,80 @@ static void test_vm_execution_ctls(void)
>         test_vmx_preemption_timer();
>  }
>
> + /*
> +  * The following checks are performed for the VM-entry MSR-load address if
> +  * the VM-entry MSR-load count field is non-zero:
> +  *
> +  *    - The lower 4 bits of the VM-entry MSR-load address must be 0.
> +  *      The address should not set any bits beyond the processor’s
> +  *      physical-address width.
> +  *
> +  *    - The address of the last byte in the VM-entry MSR-load area
> +  *      should not set any bits beyond the processor’s physical-address
> +  *      width. The address of this last byte is VM-entry MSR-load address
> +  *      + (MSR count * 16) - 1. (The arithmetic used for the computation
> +  *      uses more bits than the processor’s physical-address width.)
> +  *
> +  *
> +  *  [Intel SDM]
> +  */
> +static void test_entry_msr_load(void)
> +{
> +       entry_msr_load = alloc_page();

Type?




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