Re: [PATCH v3 16/18] kvm: x86: Flush only affected TLB entries in kvm_mmu_invlpg*

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On 18/07/2018 22:14, Junaid Shahid wrote:
> Of course, that doesn't necessarily mean that it is the architectural
> behavior for AMD vs. just an implementation detail (since
> invalidating more than the requirement is always allowed). Can we
> assume that the behavior specified in the Intel SDM for INVLPG is the
> architectural behavior for AMD as well?

Yeah, I think it's okay to assume that.  We do have some code that
(feebly) attempts to support AMD vendor CPUID on Intel and vice versa,
so there are other cases where particularly quirky vendor-specific
behavior is avoided.  For example we always assume CPL=SS.DPL, while AMD
has some cases involving SYSCALL/SYSRET for which that's not true.

Thanks,

Paolo



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