I agree that the manual is confusing in that it makes the statement under the subsection about the TSC-Deadline mode. But the statement is also used to introduce Table 10-2, which discusses all three APIC timer modes (i.e., One-shot, Periodic, and TSC-Deadline). Regardless, I found that this test fails on my system. When I dug into it, in addition to observing what the manual says, I also observed that in the KVM source code, the timer is armed when the APIC_TMICTT is written [1], whereas it is NOT armed when the APIC_LVTT register is written [2] to change the APIC timer's mode. [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/x86/kvm/lapic.c#n1801 [2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/x86/kvm/lapic.c#n1787 Thanks, Marc On Wed, Apr 4, 2018 at 5:10 PM Wanpeng Li <kernellwp@xxxxxxxxx> wrote: > 2018-04-05 7:12 GMT+08:00 Jim Mattson <jmattson@xxxxxxxxxx>: > > On Thu, Sep 28, 2017 at 6:06 PM, Wanpeng Li <kernellwp@xxxxxxxxx> wrote: > >> From: Wanpeng Li <wanpeng.li@xxxxxxxxxxx> > > > >> + /* > >> + * After the change of mode, the counter should not be reset and continue > >> + * counting down from where it was > >> + */ > > > > This seems to contradict the Intel SDM, volume 3, section 10.5.4.1: > > > > A write to the LVT Timer Register that changes the timer mode disarms > > the local APIC timer. > The statement in SDM just against TSC-Deadline Mode. > Regards, > Wanpeng Li
