> > Michael and Jason, any progress on implementing a fast virtio mechanism > > that doesn't rely on undefined behavior? > > > > (Encode writing instruction length into last 4 bits of MMIO address, > > side-channel say that accesses to the MMIO area always use certain > > instruction length, use hypercall, ...) > > > > Thanks. > > No progress from my side. But we can use PIO for virtio 1.0 and it's > faster than fast MMIO (qemu supports modern pio notification bar, we can > make it as default). It looks to me that neither encoding nor hypercall > will work for real hardware virtio device. Encoding the instruction length would work, the h/w virtio devices would just ignore it. But... it is really ugly. Using PIO would be a small step backwards for PCIe. As long as the device only needs *one* notification register (either MMIO or PIO) to initialize successfully, it's okay. Then if there is no PIO space you'd just fall back to the slower MMIO notification. Paolo
