On Mon, Nov 20, 2017 at 3:55 AM, Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote: > On Fri, 17 Nov 2017, Nadav Amit wrote: > >> CR4 changes need to be performed while IRQs are disabled in order to >> update the CR4 shadow and the actual register atomically. Actually, they >> are needed regardless of CR4 shadowing, since CR4 are performed in a >> read-modify-write manner. > > I have a hard time to figure out why that RMW protections needs to be > interrupt disable. Which call site happens to be in interrupt context? It's the flush_tlb_all() stuff. We use the cr4 accessors in the IPI handler. > > If there is none, then the proper protection is preemption disabled which > can be done without all that churn. > > Thanks, > > tglx
