On Fri, 17 Nov 2017, Nadav Amit wrote: > CR4 changes need to be performed while IRQs are disabled in order to > update the CR4 shadow and the actual register atomically. Actually, they > are needed regardless of CR4 shadowing, since CR4 are performed in a > read-modify-write manner. I have a hard time to figure out why that RMW protections needs to be interrupt disable. Which call site happens to be in interrupt context? If there is none, then the proper protection is preemption disabled which can be done without all that churn. Thanks, tglx
