On 17/10/2017 19:43, Jim Mattson wrote:
>> + &vmx_capability.ept, &vmx_capability.vpid);
>> +
>> if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
>> /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
>> enabled */
>> _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
>> CPU_BASED_CR3_STORE_EXITING |
>> CPU_BASED_INVLPG_EXITING);
>> - rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
>> - vmx_capability.ept, vmx_capability.vpid);
>> - }
>> + } else
>> + vmx_capability.ept = 0;
> I would expect vmx_capability.ept to already be 0 here. Otherwise, L0
> is reporting inconsistent VMX capabilities.
>
>> + if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID))
>> + vmx_capability.vpid = 0;
> I would expect vmx_capability.vpid to already be 0 here. Otherwise, L0
> is reporting inconsistent VMX capabilities.
>
That's true, but I think it's better to be safe. Maybe add a pr_warn if
it is not zero?
Paolo
