2017-10-04 21:21 GMT+08:00 Radim Krčmář <rkrcmar@xxxxxxxxxx>: > 2017-10-04 09:45+0800, Wanpeng Li: >> 2017-10-04 1:05 GMT+08:00 Radim Krčmář <rkrcmar@xxxxxxxxxx>: >> > 2017-09-28 18:04-0700, Wanpeng Li: >> >> From: Wanpeng Li <wanpeng.li@xxxxxxxxxxx> >> >> >> >> SDM 10.5.4.1 TSC-Deadline Mode mentioned that "Transitioning between TSC-Deadline >> >> mode and other timer modes also disarms the timer". So the APIC Timer Initial Count >> >> Register for one-shot/periodic mode should be reset. This patch do it. >> > >> > At the beginning of the secion is also: >> > >> > A write to the LVT Timer Register that changes the timer mode disarms >> > the local APIC timer. The supported timer modes are given in Table >> > 10-2. The three modes of the local APIC timer are mutually exclusive. >> >> Yeah, I saw it before sending out the patches, but it is mentioned in >> TSC-deadline section which looks strange, if the timer is still >> disarmed when switching between one-shot and periodic mode before >> TSC-deadline is introduced and w/o TSC-deadline section？ > > Yeah, maybe it is only true if the machine has TSC. APM doesn't mention If APM is another emulator? > disarming at all. Bochs only disables the timer it on switch from/to > TSC-deadline. > >> > So we should also disarm when switching between one-shot and periodic. >> > >> > apic_update_lvtt() already has logic to determine whether the timer mode >> > has changed and is the perfect place to clear APIC_TMICT. >> >> Agreed, thanks for your review, Radim. :) > > Bochs doesn't write 0 to APIC_TMICT, but it seems that Xen guys verified > that on bare-metal, so the behavior is fine. > Please just move it to apic_update_lvtt(), > > thanks. Ok, thanks for the review. :) Regards, Wanpeng Li
