> Subject: Re: [PATCH RFC 0/4] 5-level EPT > > On Thu, 29 Dec 2016 17:25:59 +0800, Liang Li said: > > x86-64 is currently limited physical address width to 46 bits, which > > can support 64 TiB of memory. Some vendors require to support more for > > some use case. Intel plans to extend the physical address width to > > 52 bits in some of the future products. > > Can you explain why this patchset mentions 52 bits in some places, and 57 in > others? Is it because there are currently in-process chipsets that will do 52, > but you want to future-proof it by extending it to 57 so future chipsets won't > need more work? Or is there some other reason? The 57-bits I referred in this patch set means the virtual address width which will be supported in the future CPU with 52-bits physical address width. 5 level EPT can support maximum 57-bits physical address width, as long as the future CPU use no more than 57-bits physical address width, no more work is needed. Thanks! Liang -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
