x86-64 is currently limited physical address width to 46 bits, which can support 64 TiB of memory. Some vendors require to support more for some use case. Intel plans to extend the physical address width to 52 bits in some of the future products. The current EPT implementation only supports 4 level page table, which can support maximum 48 bits physical address width, so it's needed to extend the EPT to 5 level to support 52 bits physical address width. This patchset has been tested in the SIMICS environment for 5 level paging guest, which was patched with Kirill's patchset for enabling 5 level page table, with both the EPT and shadow page support. I just covered the booting process, the guest can boot successfully. Some parts of this patchset can be improved. Any comments on the design or the patches would be appreciated. Liang Li (4): x86: Add the new CPUID and CR4 bits for 5 level page table KVM: MMU: Rename PT64_ROOT_LEVEL to PT64_ROOT_4LEVEL KVM: MMU: Add 5 level EPT & Shadow page table support. VMX: Expose the LA57 feature to VM arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/kvm_host.h | 15 +-- arch/x86/include/asm/vmx.h | 1 + arch/x86/include/uapi/asm/processor-flags.h | 2 + arch/x86/kvm/cpuid.c | 15 ++- arch/x86/kvm/cpuid.h | 8 ++ arch/x86/kvm/emulate.c | 15 ++- arch/x86/kvm/kvm_cache_regs.h | 7 +- arch/x86/kvm/mmu.c | 179 +++++++++++++++++++++------- arch/x86/kvm/mmu.h | 2 +- arch/x86/kvm/mmu_audit.c | 5 +- arch/x86/kvm/paging_tmpl.h | 19 ++- arch/x86/kvm/svm.c | 2 +- arch/x86/kvm/vmx.c | 23 ++-- arch/x86/kvm/x86.c | 8 +- arch/x86/kvm/x86.h | 10 ++ 16 files changed, 234 insertions(+), 78 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
