On Fri, Nov 4, 2016 at 7:50 AM, Paolo Bonzini <pbonzini@xxxxxxxxxx> wrote:
>
>
> On 02/09/2016 20:28, David Matlack wrote:
>> + case MSR_IA32_VMX_CR4_FIXED0:
>> + return vmx->nested.nested_vmx_cr4_fixed0 != data;
>> + case MSR_IA32_VMX_CR4_FIXED1:
>> + return vmx->nested.nested_vmx_cr4_fixed1 != data;
>
> Processors will have different fixed0/fixed1 as they grow support for
> new CR4 bits. The same is true for CR0, because IIRC the capability
> MSRs changed when Intel introduced unrestricted guest support.
>
> Userspace should set fixed0/fixed1 based on other execution controls
> (e.g. unrestricted guest) or CPUID (e.g. PKU, FSGSBASE, etc.), similar
> to how QEMU is doing it for CPUID leaf 0Dh (XSAVE).
>
> So I think we should accept the case where L1's fixed0/fixed1 are more
> constrained than L0's. Then handle_set_cr{0,4} can check that L1's
> fixed0/fixed1 are respected.
Agreed, I'll include that in v2.
>
> Paolo
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