On Fri, Oct 30, 2015 at 01:54:33PM -0700, Richard Henderson wrote: > On 10/29/2015 12:31 AM, Xiao Guangrong wrote: > > These instructions are used by NVDIMM drivers and the specification > > locates at: > > https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf > > > > There instructions are available on Skylake Server > > > > Signed-off-by: Xiao Guangrong <guangrong.xiao@xxxxxxxxxxxxxxx> > > --- > > target-i386/cpu.c | 8 +++++--- > > target-i386/cpu.h | 3 +++ > > 2 files changed, 8 insertions(+), 3 deletions(-) > > Reviewed-by: Richard Henderson <rth@xxxxxxxxxxx> > > Although it would be nice to update the comments in translate.c to include the > new insns, since they overlap mfence and sfence. At present we only check for > SSE enabled when accepting these; I suppose it's easiest to consider it invalid > to specify +clwb,-sse? I assume you want to add the extra SSE requirement to TCG code, not to generic x86 code, then I have no objections. Your conclusion seems to be right for pcommit and clflushopt, if I checked the opcodes and encoding properly. In the case of pcommit (/7, modrm == 0xf8), we check for SSE; in the case of clflushopt (/7 with a memory operand, modrm != 0xf8), we check for CLFLUSH. But in the case of clwb (/6 with a memory operand, modrm != 0xc0), we are not just requiring SSE2: we are rejecting the instruction unless modrm == 0xc0. That means TCG is rejecting the clwb instruction, so I believe we shouldn't add CLWB to TCG_7_0_EBX_FEATURES yet. -- Eduardo -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
