Dong, Eddie wrote:
+ case PT64_ROOT_LEVEL: + context->rsvd_bits_mask[0][3] = exb_bit_rsvd | + rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); + context->rsvd_bits_mask[0][2] = exb_bit_rsvd | + rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); + context->rsvd_bits_mask[0][1] = exb_bit_rsvd | + rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); + context->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51)
I added a test for this and it noticed the pte bits missed nx. I fixed that up. I also added code to shadow into different pages when EFER.NXE changes, so that we can handle the transition without flushing all shadow (and also run vcpus with mismatched EFER.NX).
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