>> + context->rsvd_bits_mask[0] = rsvd_bits(maxphyaddr, 51);
>> + context->large_page_rsvd_mask = /* 2MB PDE */
>> + rsvd_bits(maxphyaddr, 51) | rsvd_bits(13, 20);
>> return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL); }
>>
>
> Isn't bit 63 reserved if NX is disabled?
Sure.
>
>>
>> @@ -2206,6 +2258,18 @@ static int paging32_init_context(struct
>> kvm_vcpu *vcpu)
>>
>> static int paging32E_init_context(struct kvm_vcpu *vcpu) {
>> + struct kvm_mmu *context = &vcpu->arch.mmu;
>> + int maxphyaddr = cpuid_maxphyaddr(vcpu);
>> +
>> + /* 3 levels */
>> + context->rsvd_bits_mask[2] = rsvd_bits(maxphyaddr, 63) |
>> + rsvd_bits(7, 8) | rsvd_bits(1,2); /* PDPTE */
>>
>
> Will never be use, PDPTEs are loaded by set_cr3(), not walk_addr().
>
I see, then how about to replace CR3_PAE_RESERVED_BITS check at cr3 load with
rsvd_bits_mask[2]? Seems current code are lacking of enough reserved bits check too.
>> @@ -153,10 +154,13 @@ walk:
>> walker->level - 1, table_gfn);
>>
>> kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
>> + rsvd_fault = is_rsvd_bits_set(vcpu, pte, walker->level);
>>
>
> Does a not present pte set PFERR_RSVD?
Yes though most commercial OS doesn't use it.
I plan to post a follow up patch to fix the potential RSVD_fault error code mismatch when bypass_guest_pf=1.
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