On 2015-04-08 18:59, Nadav Amit wrote:
> Jan Kiszka <jan.kiszka@xxxxxxxxxxx> wrote:
>
>> On 2015-04-08 18:40, Nadav Amit wrote:
>>> Hi,
>>>
>>> I would appreciate if someone explains the reason for enabling LINT0 during
>>> APIC reset. This does not correspond with Intel SDM Figure 10-8: “Local
>>> Vector Table” that says all LVT registers are reset to 0x10000.
>>>
>>> In kvm_lapic_reset, I see:
>>>
>>> apic_set_reg(apic, APIC_LVT0,
>>> SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
>>>
>>> Which is actually pretty similar to QEMU’s apic_reset_common:
>>>
>>> if (bsp) {
>>> /*
>>> * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
>>> * time typically by BIOS, so PIC interrupt can be delivered to the
>>> * processor when local APIC is enabled.
>>> */
>>> s->lvt[APIC_LVT_LINT0] = 0x700;
>>> }
>>>
>>> Yet, in both cases, I miss the point - if it is typically done by the BIOS,
>>> why does QEMU or KVM enable it?
>>>
>>> BTW: KVM seems to run fine without it, and I think setting it causes me
>>> problems in certain cases.
>>
>> I suspect it has some historic BIOS backgrounds. Already tried to find
>> more information in the git logs of both code bases? Or something that
>> indicates of SeaBIOS or BochsBIOS once didn't do this initialization?
> Thanks. I found no indication of such thing.
>
> QEMU’s commit message (0e21e12bb311c4c1095d0269dc2ef81196ccb60a) says:
>
> Don't route PIC interrupts through the local APIC if the local APIC
> config says so. By Ari Kivity.
>
> Maybe Avi Kivity knows this guy.
ths? That should have been Thiemo Seufer (IIRC), but he just committed
the code back then (and is no longer with us, sadly).
But if that commit went in without any BIOS changes around it, QEMU
simply had to do the job of the latter to keep things working.
Jan
--
Siemens AG, Corporate Technology, CT RTC ITP SES-DE
Corporate Competence Center Embedded Linux
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