Re: 2 CPU Conformance Issue in KVM/x86

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On 03/09/2015 09:38 PM, Paolo Bonzini wrote:

On 09/03/2015 20:19, Avi Kivity wrote:
I can't think of one with reasonable performance either.  Perhaps the
maintainers could raise the issue with Intel.  It looks academic but it
can happen in real life -- KVM for example used to rely on reserved bits
faults (it set all bits in the PTE so it wouldn't have been caught by
this).
Yes, and it checked that MAXPHYADDR != 52 before.  If you want to set
only one bit, making that bit 51 makes sense anyway for simplicity, so
it is still 99.9% academic.  Once processors appear with MAXPHYADDR =
52, the remaining 0.1% will become more relevant.

The current limit is IIRC 46 or 48 (on Haswell Xeons).


It will be interesting to have processors with 52 bits of physical address and 48 bits of virtual address. HIGHMEM for x86_64? Or 5-level page tables?

50 bits == 1 PiB.  That's quite an amount of RAM.
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