On Thu, Jan 15, 2015 at 01:00:58PM +0000, Christoffer Dall wrote: > Hi Mark, > > On Thu, Jan 15, 2015 at 12:00:20PM +0000, Mark Rutland wrote: > > On Tue, Jan 13, 2015 at 01:35:16PM +0000, Christoffer Dall wrote: > > > On Tue, Jan 13, 2015 at 12:12:41PM +0000, Peter Maydell wrote: > > > > On 13 January 2015 at 12:04, Christoffer Dall > > > > <christoffer.dall@xxxxxxxxxx> wrote: > > > > > Additionally, I haven't been able to think of a reasonable guest > > > > > scenario where this breaks. Once the guest turns on its MMU it should > > > > > deal with the necessary icache invalidation itself (I think), so we're > > > > > really talking about situations where the stage-1 MMU is off, and I > > > > > gather that mostly you'll be seeing a single core doing any heavy > > > > > lifting and then secondary cores basically coming up, only seeing valid > > > > > entries in the icache, and doing the necessary invalidat+turn on mmu > > > > > stuff. > > > > > > > > The trouble with that is that as the secondary comes up, before it > > > > turns on its icache its VA->PA mapping is the identity map; whereas > > > > the primary vCPU's VA->PA mapping is "whatever the guest kernel's > > > > usual mapping is". If the kernel has some mapping other than identity > > > > for the VA which is wherever the secondary-CPU-startup-to-MMU-enable > > > > code lives (which seems quite likely), then you have potential problems. > > > > > > > Wouldn't a guest (and I believe Linux does this) reserve ASID 0 for > > > additional cores and use ASID 1+++ for itself? > > > > Not on arm since 52af9c6cd863fe37 (ARM: 6943/1: mm: use TTBR1 instead of > > reserved context ID) and 45b95235b0ac86ce (ARM: 6944/1: mm: allow ASID 0 > > to be allocated to tasks). The swapper_pg_dir uses global mappings since > > d427958a46af24f7 (ARM: 6942/1: mm: make TTBR1 always point to > > swapper_pg_dir on ARMv6/7). > > thanks for the pointer, been a while since I looked at that code. > > > > > Similarly on arm64 the swapper_pg_dir and idmap_pg_dir use global > > mappings and we don't reserve any ASIDs for use by the kernel. > > > > Do you happen to know which ASIDs are matched in the icache when the MMU > is off? Unfortunately not. I only seem to have derived as much as anyone else here by reading the ARM ARM. Thanks, Mark. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
