On 25/11/2014 04:15, Zhang, Yang Z wrote: > > The IRR register means an interrupt was received and not serviced yet, > > similar to the LAPIC or PIC register. It is not the same thing as the > > interrupt line level (it happens to be for level-triggered interrupts). > > Yes, but commit(0bc830b05) changes the behavior: before it , > ioapic->irr is cleared only when userspace lower the irq level. With it, > it is cleared after the edge interrupt is serviced by ioapic. As you > mentioned below, if QEMU tried to set a line twice, than there will be > two interrupts for guest which only one interrupt before commit(0bc830b05). Indeed, but that shouldn't happen. It would be a QEMU bug, since the all-QEMU implementation of the ioapic is doing the same as commit 0bc830b05. Paolo -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
