Hi Paolo, On 17/11/14 15:29, Paolo Bonzini wrote: > > > On 17/11/2014 15:58, Ard Biesheuvel wrote: >> Readonly memslots are often used to implement emulation of ROMs and >> NOR flashes, in which case the guest may legally map these regions as >> uncached. >> To deal with the incoherency associated with uncached guest mappings, >> treat all readonly memslots as incoherent, and ensure that pages that >> belong to regions tagged as such are flushed to DRAM before being passed >> to the guest. > > On x86, the processor combines the cacheability values from the two > levels of page tables. Is there no way to do the same on ARM? ARM is broadly similar, but there's a number of gotchas: - uncacheable (guest level) + cacheable (host level) -> uncacheable: the read request is going to be directly sent to RAM, bypassing the caches. - Userspace is going to use a cacheable view of the "NOR" pages, which is going to stick around in the cache (this is just memory, after all). The net result is that we need to detect those cases and make sure the guest sees the latest bit of data written by userland. We already have a similar mechanism when we fault pages in, but the guest has not enabled its caches yet. M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
