Il 18/08/2014 21:42, Nadav Amit ha scritto: > Intel SDM 10.5.4.1 says "When the timer generates an interrupt, it disarms > itself and clears the IA32_TSC_DEADLINE MSR". > > This patch clears the MSR upon timer interrupt delivery which delivered on > deadline mode. Since the MSR may be reconfigured while an interrupt is > pending, causing the new value to be overriden, pending timer interrupts are > checked before setting a new deadline. > > Signed-off-by: Nadav Amit <namit@xxxxxxxxxxxxxxxxx> > --- > arch/x86/kvm/lapic.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index 08e8a89..666c086 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -1352,6 +1352,9 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) > return; > > hrtimer_cancel(&apic->lapic_timer.timer); > + /* Inject here so clearing tscdeadline won't override new value */ > + if (apic_has_pending_timer(vcpu)) > + kvm_inject_apic_timer_irqs(vcpu); > apic->lapic_timer.tscdeadline = data; > start_apic_timer(apic); > } > @@ -1639,6 +1642,8 @@ void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) > > if (atomic_read(&apic->lapic_timer.pending) > 0) { > kvm_apic_local_deliver(apic, APIC_LVTT); > + if (apic_lvtt_tscdeadline(apic)) > + apic->lapic_timer.tscdeadline = 0; > atomic_set(&apic->lapic_timer.pending, 0); > } > } > Applied, thanks. Also applied patch 2 to kvm-unit-tests. Paolo -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html