On Fri, Jun 20, 2014 at 01:09:12PM +0300, Gleb Natapov wrote: > On Thu, Jun 19, 2014 at 04:22:57PM -0300, Marcelo Tosatti wrote: > > On Thu, Jun 19, 2014 at 10:21:16AM +0300, Gleb Natapov wrote: > > > On Wed, Jun 18, 2014 at 08:12:05PM -0300, mtosatti@xxxxxxxxxx wrote: > > > > Allow vcpus to pin spte translations by: > > > > > > > > 1) Creating a per-vcpu list of pinned ranges. > > > What if memory slot containing pinned range is going away? > > > > ->page_fault() should fail and guest abort. Will double check. > > > > > > 2) On mmu reload request: > > > > - Fault ranges. > > > > - Mark sptes with a pinned bit. > > > Should also be marked "dirty" as per SDM: > > > The three DS save area sections should be allocated from a non-paged pool, and marked accessed and dirty > > > > This (SDM text) is about guest pagetable AFAICS. > > > Its hard to say. SDM does not mention virtualization or two dimensional > paging in that section at all. My reading is that this section talks about > all translations that CPU should perform to get to the physical address, > otherwise why are we trying hard to make sure that EPT translations are > always present? Because the same paragraph say in the next sentence: > > It is the responsibility of the operating system to keep the pages that > contain the buffer present and to mark them accessed and dirty > > So it we take from it that translation should be present the same goes for > accessed and dirty. If Andi can clarify this within Intel it would be great. Andi? -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
