Hi Marc,
On Mon, Jun 30, 2014 at 04:01:32PM +0100, Marc Zyngier wrote:
> Add the necessary documentation to support GICv3.
>
> Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
> Cc: Mark Rutland <mark.rutland@xxxxxxx>
> Acked-by: Catalin Marinas <catalin.marinas@xxxxxxx>
> Acked-by: Rob Herring <robh@xxxxxxxxxx>
> Acked-by: Christoffer Dall <christoffer.dall@xxxxxxxxxx>
> Signed-off-by: Marc Zyngier <marc.zyngier@xxxxxxx>
No-one's prepared to say they reviewed this?
Let's fix that ;)
Reviewed-by: Mark Rutland <mark.rutland@xxxxxxx>
Thanks,
Mark.
> ---
> Documentation/devicetree/bindings/arm/gic-v3.txt | 79 ++++++++++++++++++++++++
> 1 file changed, 79 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/gic-v3.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/gic-v3.txt b/Documentation/devicetree/bindings/arm/gic-v3.txt
> new file mode 100644
> index 0000000..33cd05e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/gic-v3.txt
> @@ -0,0 +1,79 @@
> +* ARM Generic Interrupt Controller, version 3
> +
> +AArch64 SMP cores are often associated with a GICv3, providing Private
> +Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
> +Software Generated Interrupts (SGI), and Locality-specific Peripheral
> +Interrupts (LPI).
> +
> +Main node required properties:
> +
> +- compatible : should at least contain "arm,gic-v3".
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> + interrupt source. Must be a single cell with a value of at least 3.
> +
> + The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
> + interrupts. Other values are reserved for future use.
> +
> + The 2nd cell contains the interrupt number for the interrupt type.
> + SPI interrupts are in the range [0-987]. PPI interrupts are in the
> + range [0-15].
> +
> + The 3rd cell is the flags, encoded as follows:
> + bits[3:0] trigger type and level flags.
> + 1 = edge triggered
> + 4 = level triggered
> +
> + Cells 4 and beyond are reserved for future use. When the 1st cell
> + has a value of 0 or 1, cells 4 and beyond act as padding, and may be
> + ignored. It is recommended that padding cells have a value of 0.
> +
> +- reg : Specifies base physical address(s) and size of the GIC
> + registers, in the following order:
> + - GIC Distributor interface (GICD)
> + - GIC Redistributors (GICR), one range per redistributor region
> + - GIC CPU interface (GICC)
> + - GIC Hypervisor interface (GICH)
> + - GIC Virtual CPU interface (GICV)
> +
> + GICC, GICH and GICV are optional.
> +
> +- interrupts : Interrupt source of the VGIC maintenance interrupt.
> +
> +Optional
> +
> +- redistributor-stride : If using padding pages, specifies the stride
> + of consecutive redistributors. Must be a multiple of 64kB.
> +
> +- #redistributor-regions: The number of independent contiguous regions
> + occupied by the redistributors. Required if more than one such
> + region is present.
> +
> +Examples:
> +
> + gic: interrupt-controller@2cf00000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x2f000000 0 0x10000>, // GICD
> + <0x0 0x2f100000 0 0x200000>, // GICR
> + <0x0 0x2c000000 0 0x2000>, // GICC
> + <0x0 0x2c010000 0 0x2000>, // GICH
> + <0x0 0x2c020000 0 0x2000>; // GICV
> + interrupts = <1 9 4>;
> + };
> +
> + gic: interrupt-controller@2c010000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + redistributor-stride = <0x0 0x40000>; // 256kB stride
> + #redistributor-regions = <2>;
> + reg = <0x0 0x2c010000 0 0x10000>, // GICD
> + <0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31
> + <0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63
> + <0x0 0x2c040000 0 0x2000>, // GICC
> + <0x0 0x2c060000 0 0x2000>, // GICH
> + <0x0 0x2c080000 0 0x2000>; // GICV
> + interrupts = <1 9 4>;
> + };
> --
> 2.0.0
>
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