Re: How does kvm support x2apic?

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On Tue, Jun 10, 2014 at 9:33 PM, Zhang Haoyu <zhanghy@xxxxxxxxxxx> wrote:
>> Hi,
>>
>> According to this:
>>
>> https://github.com/torvalds/linux/commit/0d1de2d901f4ba0972a3886496a44fb1d3300dbd
>>
>> It looks like kvm have been supporting x2apic since kernel 2.6.32, or
>> even earlier.
>>
> This patch is to emulate x2apic for guest, then guest can benefit from some advantages of x2apic, like using RDMSR/WRMSR instead of mmio.
>
>> However, this following patch:
>>
>> https://github.com/torvalds/linux/commit/8d14695f9542e9e0195d6e41ddaa52c32322adf5
>>
>> Also claims that adding support for x2apic. But this later patch was
>> for kernel 3.9.
> This patch is to support virtual x2apic mode, which can virtualizing MSR-based APIC accesses by configuring MSR bitmaps,
> you can specify some MSR-based accesses without VM exit, the other MSR-based accesses with VM exit,
> which belongs to APIC virtualization from certain angle.
Thanks Haoyu, I am reading the Intel x2apic manual.

http://www.intel.com/content/dam/doc/specification-update/64-architecture-x2apic-specification.pdf

but I don't see the so called "virtual x2apic mode", it seems that the
manual does not mention anything about that. Do you mean that when the
Guest OS sets bit 10 (x2apic mode enable bit) of the it virtualized
IA32_APIC_BASE MSR, it is entering a virtual x2apic mode? But isn't
this the same as the aforementioned "emulate x2apic for guest"? Or,
"emulate x2apic for guest" is the foundation of "support virtual
x2apic mode"?

-Jidong

>>
>> So I am very confused:
>>
>> First, what's the difference between these two patches? Or say, does
>> kvm support x2apic since kernel 2.6.32, or since kernel 3.9?
>>
> kvm support x2apic since kernel 2.6.32, but not support virtual x2apic mode until kernel 3.9.
>
>> Second, can guest use x2apic even if the host does not? (Assuming qemu
>>has exposed this feature to guest.) The word "use" means something
>> like, accessing x2apic registers, setting the x2apic enable bit in
>> IA32_APICBASE MSR (i.e. bit 10).
>>
> Yes, you can use x2apic even if the PCPU does not support, and benefit from it, like performance bonus from MSR accesses instead of MMIO.
> But, if I remember correctly, if your guest does not support interrupt-remmping, you only can use physical destination mode when using x2apic,
> please see enable_IR_x2apic().
>
>> -Jidong
>
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