Hi David, On Friday 25 April 2014 09:36:50 David Daney wrote: > On 04/25/2014 08:19 AM, James Hogan wrote: > > -#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) > > +#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_32(15, 1) > > According to: > > MIPS® Architecture Reference Manual > Volume III: The MIPS64® and > microMIPS64TM Privileged Resource > Architecture > > Document Number: MD00089 > Revision 5.02 > April 30, 2013 > > In section 9.39 EBase Register (CP0 Register 15, Select 1), we see that > EBase can be either 32-bits or 64-bits wide. > > I would recommend leaving this as a 64-bit wide register, so that CPU > implementations with the wider EBase can be supported. Yes, you're quite right. I should have checked that one for carefully (I did think it was a bit odd for it to be 32bit on MIPS64). I'll drop this patch. Thanks James > > Alternately, probe for the width and use the appropriate 32-bit or > 64-bit to more closely reflect reality. > > > #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) > > #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) > > #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
Attachment:
signature.asc
Description: This is a digitally signed message part.
