On 04/25/2014 08:19 AM, James Hogan wrote:
KVM_REG_MIPS_CP0_EBASE is defined as 64bit, but is a 32bit register even
in MIPS64, so fix the definition.
Note, this definition isn't actually used yet, so it didn't cause any
problems.
Signed-off-by: James Hogan <james.hogan@xxxxxxxxxx>
Cc: Paolo Bonzini <pbonzini@xxxxxxxxxx>
Cc: Gleb Natapov <gleb@xxxxxxxxxx>
Cc: kvm@xxxxxxxxxxxxxxx
Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Cc: linux-mips@xxxxxxxxxxxxxx
Cc: David Daney <david.daney@xxxxxxxxxx>
Cc: Sanjay Lal <sanjayl@xxxxxxxxxxx>
---
arch/mips/kvm/kvm_mips.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c
index 14511138f187..46cea0bad518 100644
--- a/arch/mips/kvm/kvm_mips.c
+++ b/arch/mips/kvm/kvm_mips.c
@@ -512,7 +512,7 @@ kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
-#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
+#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_32(15, 1)
According to:
MIPS® Architecture Reference Manual
Volume III: The MIPS64® and
microMIPS64TM Privileged Resource
Architecture
Document Number: MD00089
Revision 5.02
April 30, 2013
In section 9.39 EBase Register (CP0 Register 15, Select 1), we see that
EBase can be either 32-bits or 64-bits wide.
I would recommend leaving this as a 64-bit wide register, so that CPU
implementations with the wider EBase can be supported.
Alternately, probe for the width and use the appropriate 32-bit or
64-bit to more closely reflect reality.
#define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
#define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
#define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
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