On Thu, 2019-06-20 at 06:00:40 UTC, Michael Neuling wrote: > When emulating tsr, treclaim and trechkpt, we incorrectly set CR0. The > code currently sets: > CR0 <- 00 || MSR[TS] > but according to the ISA it should be: > CR0 <- 0 || MSR[TS] || 0 > > This fixes the bit shift to put the bits in the correct location. > > Tested-by: Suraj Jitindar Singh <sjitindarsingh@xxxxxxxxx> > Signed-off-by: Michael Neuling <mikey@xxxxxxxxxxx> Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/3fefd1cd95df04da67c83c1cb93b663f04b3324f cheers
