On Fri, Oct 28, 2022 at 11:53:49AM +0100, Marc Zyngier wrote: > Align the ID_DFR0_EL1.PerfMon values with ID_AA64DFR0_EL1.PMUver. > > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> Reviewed-by: Oliver Upton <oliver.upton@xxxxxxxxx> FYI, another pile of ID reg changes is on the way that'll move DFR0 to a generated definition. https://lore.kernel.org/linux-arm-kernel/20220930140211.3215348-1-james.morse@xxxxxxx/ -- Thanks, Oliver > --- > arch/arm64/include/asm/sysreg.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 7d301700d1a9..84f59ce1dc6d 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -698,6 +698,8 @@ > #define ID_DFR0_PERFMON_8_1 0x4 > #define ID_DFR0_PERFMON_8_4 0x5 > #define ID_DFR0_PERFMON_8_5 0x6 > +#define ID_DFR0_PERFMON_8_7 0x7 > +#define ID_DFR0_PERFMON_IMP_DEF 0xf > > #define ID_ISAR4_SWP_FRAC_SHIFT 28 > #define ID_ISAR4_PSR_M_SHIFT 24 > -- > 2.34.1 > _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
