Ricardo reported[0] that our PMU emulation was busted when it comes to
chained events, as we cannot expose the overflow on a 32bit boundary
(which the architecture requires).
This series aims at fixing this (by deleting a lot of code), and as a
bonus adds support for PMUv3p5, as this requires us to fix a few more
things.
Tested on A53 (PMUv3) and QEMU (PMUv3p5).
* From v1 [1]:
- Rebased on 6.1-rc2
- New patch advertising that we always support the CHAIN event
- Plenty of bug fixes (idreg handling, AArch32, overflow narrowing)
- Tons of cleanups
- All kudos to Oliver and Reiji for spending the time to review this
mess, and Ricardo for finding more bugs!
[0] https://lore.kernel.org/r/20220805004139.990531-1-ricarkol@xxxxxxxxxx
[1] https://lore.kernel.org/r/20220805135813.2102034-1-maz@xxxxxxxxxx
Marc Zyngier (14):
arm64: Add ID_DFR0_EL1.PerfMon values for PMUv3p7 and IMP_DEF
KVM: arm64: PMU: Align chained counter implementation with
architecture pseudocode
KVM: arm64: PMU: Always advertise the CHAIN event
KVM: arm64: PMU: Distinguish between 64bit counter and 64bit overflow
KVM: arm64: PMU: Narrow the overflow checking when required
KVM: arm64: PMU: Only narrow counters that are not 64bit wide
KVM: arm64: PMU: Add counter_index_to_*reg() helpers
KVM: arm64: PMU: Simplify setting a counter to a specific value
KVM: arm64: PMU: Do not let AArch32 change the counters' top 32 bits
KVM: arm64: PMU: Move the ID_AA64DFR0_EL1.PMUver limit to VM creation
KVM: arm64: PMU: Allow ID_AA64DFR0_EL1.PMUver to be set from userspace
KVM: arm64: PMU: Allow ID_DFR0_EL1.PerfMon to be set from userspace
KVM: arm64: PMU: Implement PMUv3p5 long counter support
KVM: arm64: PMU: Allow PMUv3p5 to be exposed to the guest
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/include/asm/sysreg.h | 2 +
arch/arm64/kvm/arm.c | 6 +
arch/arm64/kvm/pmu-emul.c | 408 ++++++++++++------------------
arch/arm64/kvm/sys_regs.c | 135 +++++++++-
include/kvm/arm_pmu.h | 15 +-
6 files changed, 307 insertions(+), 260 deletions(-)
--
2.34.1
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