On Sat, May 14, 2022 at 11:25:24AM +0100, Marc Zyngier wrote: > Unsusprisingly, Apple M1 Pro/Max have the exact same defect as the > original M1 and generate random SErrors in the host when a guest > tickles the GICv3 CPU interface the wrong way. > > Add the part numbers for both the CPU types found in these two > new implementations, and add them to the hall of shame. This also > applies to the Ultra version, as it is composed of 2 Max SoCs. > > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> > --- > arch/arm64/include/asm/cputype.h | 8 ++++++++ > arch/arm64/kvm/vgic/vgic-v3.c | 4 ++++ > 2 files changed, 12 insertions(+) > > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > index ff8f4511df71..60647bdc0b09 100644 > --- a/arch/arm64/include/asm/cputype.h > +++ b/arch/arm64/include/asm/cputype.h > @@ -118,6 +118,10 @@ > > #define APPLE_CPU_PART_M1_ICESTORM 0x022 > #define APPLE_CPU_PART_M1_FIRESTORM 0x023 > +#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024 > +#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025 > +#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028 > +#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029 > > #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) > #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) > @@ -164,6 +168,10 @@ > #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) > #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM) > #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM) > +#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO) > +#define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO) > +#define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX) > +#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX) Acked-by: Catalin Marinas <catalin.marinas@xxxxxxx> _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
