On Tue, Aug 10, 2021 at 09:59:42AM +0530, Anshuman Khandual wrote: > Streamline the Stage-2 TGRAN value extraction from ID_AA64MMFR0 register by > adding a page size agnostic ID_AA64MMFR0_TGRAN_2_SHIFT. This is similar to > the existing Stage-1 TGRAN shift i.e ID_AA64MMFR0_TGRAN_SHIFT. > > Cc: Catalin Marinas <catalin.marinas@xxxxxxx> > Cc: Will Deacon <will@xxxxxxxxxx> > Cc: Marc Zyngier <maz@xxxxxxxxxx> > Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx > Cc: kvmarm@xxxxxxxxxxxxxxxxxxxxx > Cc: linux-kernel@xxxxxxxxxxxxxxx > Signed-off-by: Anshuman Khandual <anshuman.khandual@xxxxxxx> > --- > This applies on v5.14-rc5. > > arch/arm64/include/asm/sysreg.h | 3 +++ > arch/arm64/kvm/reset.c | 17 ++--------------- > 2 files changed, 5 insertions(+), 15 deletions(-) Acked-by: Will Deacon <will@xxxxxxxxxx> Will _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
