Argh, forgot to CC Eric.
On 6/18/21 11:51 AM, Alexandru Elisei wrote:
> According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to
> 1 has the following effect:
>
> "Reset all event counters accessible in the current Exception level, not
> including PMCCNTR_EL0, to zero."
>
> Similar behaviour is described for AArch32 on page G8-7022. Make it so.
>
> Fixes: c01d6a18023b ("KVM: arm64: pmu: Only handle supported event counters")
> Signed-off-by: Alexandru Elisei <alexandru.elisei@xxxxxxx>
> ---
> Found by code inspection.
>
> Entertained the idea of restricting the number of bits in
> for_each_set_bit() to 31 since Linux (and the architecture, to some degree)
> treats the cycle count register as the 32nd event counter. Settled on this
> approach because I think it's clearer.
>
> arch/arm64/kvm/pmu-emul.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
> index fd167d4f4215..ecc0d19c8cc1 100644
> --- a/arch/arm64/kvm/pmu-emul.c
> +++ b/arch/arm64/kvm/pmu-emul.c
> @@ -578,6 +578,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
> kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);
>
> if (val & ARMV8_PMU_PMCR_P) {
> + mask &= ~BIT(ARMV8_PMU_CYCLE_IDX);
> for_each_set_bit(i, &mask, 32)
> kvm_pmu_set_counter_value(vcpu, i, 0);
> }
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