Add 2 tests exercising chained counters. The first one uses
CPU_CYCLES and the second one uses SW_INCR.
Signed-off-by: Eric Auger <eric.auger@xxxxxxxxxx>
---
v3 -> v4:
- each report_info has a different message
v2 -> v3:
- added prefix pop
- added pmu prefix to the test names
- defines, event array ...
---
arm/pmu.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++-
arm/unittests.cfg | 12 ++++++
2 files changed, 109 insertions(+), 1 deletion(-)
diff --git a/arm/pmu.c b/arm/pmu.c
index c954c71..be249cc 100644
--- a/arm/pmu.c
+++ b/arm/pmu.c
@@ -47,6 +47,7 @@
#define INST_PREC 0x1B
#define STALL_FRONTEND 0x23
#define STALL_BACKEND 0x24
+#define CHAIN 0x1E
#define COMMON_EVENTS_LOW 0x0
#define COMMON_EVENTS_HIGH 0x3F
@@ -141,6 +142,8 @@ static void test_event_counter_config(void) {}
static void test_basic_event_count(void) {}
static void test_mem_access(void) {}
static void test_sw_incr(void) {}
+static void test_chained_counters(void) {}
+static void test_chained_sw_incr(void) {}
#elif defined(__aarch64__)
#define ID_AA64DFR0_PERFMON_SHIFT 8
@@ -504,7 +507,92 @@ static void test_sw_incr(void)
report_info("counter values after 100 SW_INCR #0=%ld #1=%ld",
read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));
report(read_sysreg(pmovsclr_el0) == 0x1,
- "overflow reg after 100 SW_INCR");
+ "overflow on counter #0 after 100 SW_INCR");
+}
+
+static void test_chained_counters(void)
+{
+ uint32_t events[] = {CPU_CYCLES, CHAIN};
+
+ if (!satisfy_prerequisites(events, ARRAY_SIZE(events)))
+ return;
+
+ pmu_reset();
+
+ write_regn_el0(pmevtyper, 0, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0);
+ write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0);
+ /* enable counters #0 and #1 */
+ write_sysreg_s(0x3, PMCNTENSET_EL0);
+ write_regn_el0(pmevcntr, 0, PRE_OVERFLOW);
+
+ precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E);
+
+ report(read_regn_el0(pmevcntr, 1) == 1, "CHAIN counter #1 incremented");
+ report(!read_sysreg(pmovsclr_el0), "no overflow recorded for chained incr #1");
+
+ /* test 64b overflow */
+
+ pmu_reset();
+ write_sysreg_s(0x3, PMCNTENSET_EL0);
+
+ write_regn_el0(pmevcntr, 0, PRE_OVERFLOW);
+ write_regn_el0(pmevcntr, 1, 0x1);
+ precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E);
+ report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0));
+ report(read_regn_el0(pmevcntr, 1) == 2, "CHAIN counter #1 set to 2");
+ report(!read_sysreg(pmovsclr_el0), "no overflow recorded for chained incr #2");
+
+ write_regn_el0(pmevcntr, 0, PRE_OVERFLOW);
+ write_regn_el0(pmevcntr, 1, ALL_SET);
+
+ precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E);
+ report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0));
+ report(!read_regn_el0(pmevcntr, 1), "CHAIN counter #1 wrapped");
+ report(read_sysreg(pmovsclr_el0) == 0x2, "overflow on chain counter");
+}
+
+static void test_chained_sw_incr(void)
+{
+ uint32_t events[] = {SW_INCR, CHAIN};
+ int i;
+
+ if (!satisfy_prerequisites(events, ARRAY_SIZE(events)))
+ return;
+
+ pmu_reset();
+
+ write_regn_el0(pmevtyper, 0, SW_INCR | PMEVTYPER_EXCLUDE_EL0);
+ write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0);
+ /* enable counters #0 and #1 */
+ write_sysreg_s(0x3, PMCNTENSET_EL0);
+
+ write_regn_el0(pmevcntr, 0, PRE_OVERFLOW);
+ set_pmcr(pmu.pmcr_ro | PMU_PMCR_E);
+ for (i = 0; i < 100; i++)
+ write_sysreg(0x1, pmswinc_el0);
+
+ report(!read_sysreg(pmovsclr_el0) && (read_regn_el0(pmevcntr, 1) == 1),
+ "no overflow and chain counter incremented after 100 SW_INCR/CHAIN");
+ report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0),
+ read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));
+
+ /* 64b SW_INCR and overflow on CHAIN counter*/
+ pmu_reset();
+
+ write_regn_el0(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0);
+ write_regn_el0(pmevcntr, 0, PRE_OVERFLOW);
+ write_regn_el0(pmevcntr, 1, ALL_SET);
+ write_sysreg_s(0x3, PMCNTENSET_EL0);
+ set_pmcr(pmu.pmcr_ro | PMU_PMCR_E);
+ for (i = 0; i < 100; i++)
+ write_sysreg(0x1, pmswinc_el0);
+
+ report((read_sysreg(pmovsclr_el0) == 0x2) &&
+ (read_regn_el0(pmevcntr, 1) == 0) &&
+ (read_regn_el0(pmevcntr, 0) == 84),
+ "overflow on chain counter and expected values after 100 SW_INCR/CHAIN");
+ report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0),
+ read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));
}
#endif
@@ -697,6 +785,14 @@ int main(int argc, char *argv[])
report_prefix_push(argv[1]);
test_sw_incr();
report_prefix_pop();
+ } else if (strcmp(argv[1], "pmu-chained-counters") == 0) {
+ report_prefix_push(argv[1]);
+ test_chained_counters();
+ report_prefix_pop();
+ } else if (strcmp(argv[1], "pmu-chained-sw-incr") == 0) {
+ report_prefix_push(argv[1]);
+ test_chained_sw_incr();
+ report_prefix_pop();
} else {
report_abort("Unknown sub-test '%s'", argv[1]);
}
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index 175afe6..d31dcbf 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -96,6 +96,18 @@ groups = pmu
arch = arm64
extra_params = -append 'pmu-sw-incr'
+[pmu-chained-counters]
+file = pmu.flat
+groups = pmu
+arch = arm64
+extra_params = -append 'pmu-chained-counters'
+
+[pmu-chained-sw-incr]
+file = pmu.flat
+groups = pmu
+arch = arm64
+extra_params = -append 'pmu-chained-sw-incr'
+
# Test PMU support (TCG) with -icount IPC=1
#[pmu-tcg-icount-1]
#file = pmu.flat
--
2.20.1
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