Add tests dedicated to SW_INCR event counting.
Signed-off-by: Eric Auger <eric.auger@xxxxxxxxxx>
---
v3: new
- Formerly in chained counter tests but as QEMU does not
support chained counters, the whole test was failing. Peter
split the test.
---
arm/pmu.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
arm/unittests.cfg | 6 ++++++
2 files changed, 53 insertions(+)
diff --git a/arm/pmu.c b/arm/pmu.c
index 45dccf7..c954c71 100644
--- a/arm/pmu.c
+++ b/arm/pmu.c
@@ -140,6 +140,7 @@ static void test_event_introspection(void) {}
static void test_event_counter_config(void) {}
static void test_basic_event_count(void) {}
static void test_mem_access(void) {}
+static void test_sw_incr(void) {}
#elif defined(__aarch64__)
#define ID_AA64DFR0_PERFMON_SHIFT 8
@@ -464,6 +465,48 @@ static void test_mem_access(void)
read_sysreg(pmovsclr_el0));
}
+static void test_sw_incr(void)
+{
+ uint32_t events[] = {SW_INCR, SW_INCR};
+ int i;
+
+ if (!satisfy_prerequisites(events, ARRAY_SIZE(events)))
+ return;
+
+ pmu_reset();
+
+ write_regn_el0(pmevtyper, 0, SW_INCR | PMEVTYPER_EXCLUDE_EL0);
+ write_regn_el0(pmevtyper, 1, SW_INCR | PMEVTYPER_EXCLUDE_EL0);
+ /* enable counters #0 and #1 */
+ write_sysreg_s(0x3, PMCNTENSET_EL0);
+
+ write_regn_el0(pmevcntr, 0, PRE_OVERFLOW);
+
+ for (i = 0; i < 100; i++)
+ write_sysreg(0x1, pmswinc_el0);
+
+ report_info("SW_INCR counter #0 has value %ld", read_regn_el0(pmevcntr, 0));
+ report(read_regn_el0(pmevcntr, 0) == PRE_OVERFLOW,
+ "PWSYNC does not increment if PMCR.E is unset");
+
+ pmu_reset();
+
+ write_regn_el0(pmevcntr, 0, PRE_OVERFLOW);
+ write_sysreg_s(0x3, PMCNTENSET_EL0);
+ set_pmcr(pmu.pmcr_ro | PMU_PMCR_E);
+
+ for (i = 0; i < 100; i++)
+ write_sysreg(0x3, pmswinc_el0);
+
+ report(read_regn_el0(pmevcntr, 0) == 84, "counter #1 after + 100 SW_INCR");
+ report(read_regn_el0(pmevcntr, 1) == 100,
+ "counter #0 after + 100 SW_INCR");
+ report_info("counter values after 100 SW_INCR #0=%ld #1=%ld",
+ read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));
+ report(read_sysreg(pmovsclr_el0) == 0x1,
+ "overflow reg after 100 SW_INCR");
+}
+
#endif
/*
@@ -650,6 +693,10 @@ int main(int argc, char *argv[])
report_prefix_push(argv[1]);
test_mem_access();
report_prefix_pop();
+ } else if (strcmp(argv[1], "pmu-sw-incr") == 0) {
+ report_prefix_push(argv[1]);
+ test_sw_incr();
+ report_prefix_pop();
} else {
report_abort("Unknown sub-test '%s'", argv[1]);
}
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index 32ab8c6..175afe6 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -90,6 +90,12 @@ groups = pmu
arch = arm64
extra_params = -append 'pmu-mem-access'
+[pmu-sw-incr]
+file = pmu.flat
+groups = pmu
+arch = arm64
+extra_params = -append 'pmu-sw-incr'
+
# Test PMU support (TCG) with -icount IPC=1
#[pmu-tcg-icount-1]
#file = pmu.flat
--
2.20.1
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