On Fri, Mar 27, 2020 at 05:52:59PM +0000, Marc Zyngier wrote: > On 2020-03-27 17:48, Andrew Scull wrote: > > Thanks, Steven. Could we look into the EPD* caching microarch details > > Marc was referring to for these A55 and A76 cores? > > Only the folks that have access to the RTL can tell you, unfortunately. > > Thankfully, there is a bunch of people on Cc that should be able to ping > the relevant teams and report back... Yup, otherwise I guess we can throw in the TLB invalidation after setting the EPDx bits until we have clarity from Arm. We wouldn't need to broadcast it, so it might not be too bad on performance. If it is, I suppose we could switch to a reserved VMID? Will _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
