Thanks, Steven. Could we look into the EPD* caching microarch details Marc was referring to for these A55 and A76 cores? If the behaviour is the same as A57/A72 then it sounds safe. Otherwise, there'll need to be some invalidation to avoid that issue. And thanks for the pointer to your previous patch, it's a very helpful reference. _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
