On Mon, 28 Oct 2019 13:05:41 +0000, Christoffer Dall <christoffer.dall@xxxxxxx> wrote: > > On CPUs that support S2FWB (Armv8.4+), KVM configures the stage 2 page > tables to override the memory attributes of memory accesses, regardless > of the stage 1 page table configurations, and also when the stage 1 MMU > is turned off. This results in all memory accesses to RAM being > cacheable, including during early boot of the guest. > > On CPUs without this feature, memory accesses were non-cacheable during > boot until the guest turned on the stage 1 MMU, and we had to detect > when the guest turned on the MMU, such that we could invalidate all cache > entries and ensure a consistent view of memory with the MMU turned on. > When the guest turned on the caches, we would call stage2_flush_vm() > from kvm_toggle_cache(). > > However, stage2_flush_vm() walks all the stage 2 tables, and calls > __kvm_flush-dcache_pte, which on a system with S2FWD does ... absolutely s/FWD/FWB/ > nothing. > > We can avoid that whole song and dance, and simply not set TVM when > creating a VM on a system that has S2FWB. > > Signed-off-by: Christoffer Dall <christoffer.dall@xxxxxxx> > Reviewed-by: Mark Rutland <mark.rutland@xxxxxxx> Apart from the nit above, and Mark's other remark, it looks good to me. I'll fix them up when applying the patch. Thanks, M. -- Jazz is not dead, it just smells funny. _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
