On Mon, Oct 28, 2019 at 02:05:41PM +0100, Christoffer Dall wrote:
> On CPUs that support S2FWB (Armv8.4+), KVM configures the stage 2 page
> tables to override the memory attributes of memory accesses, regardless
> of the stage 1 page table configurations, and also when the stage 1 MMU
> is turned off. This results in all memory accesses to RAM being
> cacheable, including during early boot of the guest.
>
> On CPUs without this feature, memory accesses were non-cacheable during
> boot until the guest turned on the stage 1 MMU, and we had to detect
> when the guest turned on the MMU, such that we could invalidate all cache
> entries and ensure a consistent view of memory with the MMU turned on.
> When the guest turned on the caches, we would call stage2_flush_vm()
> from kvm_toggle_cache().
>
> However, stage2_flush_vm() walks all the stage 2 tables, and calls
> __kvm_flush-dcache_pte, which on a system with S2FWD does ... absolutely
> nothing.
>
> We can avoid that whole song and dance, and simply not set TVM when
> creating a VM on a system that has S2FWB.
>
> Signed-off-by: Christoffer Dall <christoffer.dall@xxxxxxx>
> Reviewed-by: Mark Rutland <mark.rutland@xxxxxxx>
> ---
> I was only able to test this on the model with cache modeling enabled,
> but even removing TVM from HCR_EL2 without having FWB also worked with
> that setup, so the testing of this has been light. It seems like it
> should obviously work, but it would be good if someone with access to
> appropriate hardware could give this a spin.
>
> arch/arm64/include/asm/kvm_arm.h | 3 +--
> arch/arm64/include/asm/kvm_emulate.h | 12 +++++++++++-
> 2 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
> index ddf9d762ac62..6e5d839f42b5 100644
> --- a/arch/arm64/include/asm/kvm_arm.h
> +++ b/arch/arm64/include/asm/kvm_arm.h
> @@ -61,7 +61,6 @@
> * RW: 64bit by default, can be overridden for 32bit VMs
> * TAC: Trap ACTLR
> * TSC: Trap SMC
> - * TVM: Trap VM ops (until M+C set in SCTLR_EL1)
> * TSW: Trap cache operations by set/way
> * TWE: Trap WFE
> * TWI: Trap WFI
> @@ -74,7 +73,7 @@
> * SWIO: Turn set/way invalidates into set/way clean+invalidate
> */
> #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
> - HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
> + HCR_BSU_IS | HCR_FB | HCR_TAC | \
> HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
> HCR_FMO | HCR_IMO)
> #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
> diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
> index d69c1efc63e7..70509799a2a9 100644
> --- a/arch/arm64/include/asm/kvm_emulate.h
> +++ b/arch/arm64/include/asm/kvm_emulate.h
> @@ -53,8 +53,18 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
> /* trap error record accesses */
> vcpu->arch.hcr_el2 |= HCR_TERR;
> }
> - if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
> +
> + if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) {
> vcpu->arch.hcr_el2 |= HCR_FWB;
> + } else {
> + /*
> + * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C
> + * get set in SCTLR_EL1 such that we can detect when the guest
> + * MMU gets turned off and do the necessary cache maintenance
Typo: s/off/on/ -- this is to make sure the accesses made when the MMU
was off (which aren't cacheable) are visible once the MMU is turned on
(e.g. not shadowed by stale clean cache lines).
Otherwise, this looks goot to me, and my R-B stands.
Thanks,
Mark.
> + * then.
> + */
> + vcpu->arch.hcr_el2 &= ~HCR_TVM;
> + }
>
> if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features))
> vcpu->arch.hcr_el2 &= ~HCR_RW;
> --
> 2.18.0
>
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