On Mon, 28 Oct 2019 09:34:42 +0000, Zenghui Yu <yuzenghui@xxxxxxxxxx> wrote: > > Hi Marc, > > On 2019/10/27 22:42, Marc Zyngier wrote: > > Instead of caching the GICv4 compatibility in a discrete way, cache the > > TYPER register instead, which can then be used to implement the same > > functionnality. This will get used more extensively in subsequent patches. > > > > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> > > nit: You may need to rebase some patches on top of mainline when > you finally decide to take them in, i.e., as we currently have > get_its_list(), which will use the legacy its->is_v4. Yeah, I was planning on rebasing the whole irqchip-next branch on top of -rc5 to avoid this kind of problems. > Reviewed-by: Zenghui Yu <yuzenghui@xxxxxxxxxx> Thanks for that. M. -- Jazz is not dead, it just smells funny. _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
