On Thu, Sep 19, 2019 at 09:07:15PM +0800, Guo Ren wrote: > > The solution I had to this problem is pinning the ASID [1] used by the > > IOMMU, to prevent the CPU from recycling the ASID on rollover. This way > > the CPU doesn't have to wait for IOMMU invalidations to complete, when > > scheduling a task that might not even have anything to do with the IOMMU. > > > > > In the Arm SMMU, ASID and IOASID (PASID) are separate identifiers. IOASID > > indexes an entry in the context descriptor table, which contains the ASID. > > So with unpinned shared ASID you don't need to invalidate the ATC on > > rollover, since the IOASID doesn't change, but you do need to modify the > > context descriptor and invalidate cached versions of it. > The terminology confused me a lot. I perfer use PASID for IOMMU and > ASID is for CPU. > Arm's entry of the context descriptor table contains a "IOASID" The terminology I've been using so far is different: * IOASID is PASID * The entry in the context descriptor table contains an ASID, which is either "shared" with CPUs or "private" to the SMMU (the SMMU spec says "shared" or "non-shared"). * So the CPU and SMMU TLBs use ASIDs, and the PCI ATC uses IOASID > IOASID != ASID for CPU_TLB and IOMMU_TLB. > > When you say "since the IOASID doesn't change",Is it PASID or my IOASID ? -_*! I was talking about PASID. Maybe we can drop "IOASID" and talk only about ASID and PASID :) > PASID in PCI-sig was used to determine transfer address space. > For intel, the entry which is indexed by PASID also contain S1/S2.PGD > and DID(VMID). > For arm, the entry which is indexed by PASID only contain S1.PGD and > IOASID. Compare to Intel Vt-d Scalable mode, arm's design can't > support PCI Virtual Function. The SMMU does support PCI Virtual Function - an hypervisor can assign a VF to a guest, and let that guest partition the VF into smaller contexts by using PASID. What it can't support is assigning partitions of a PCI function (VF or PF) to multiple Virtual Machines, since there is a single S2 PGD per function (in the Stream Table Entry), rather than one S2 PGD per PASID context. Thanks, Jean > > Once you have pinned ASIDs, you could also declare that IOASID = ASID. I > > don't remember finding an argument to strictly forbid it, even though ASID > > and IOASID have different sizes on Arm (respectively 8/16 and 20 bits). > ASID and IOASID are hard to keep the same between CPU system and IOMMU > system. So I introduce S1/S2.PGD.PPN as a bridge between CPUs and > IOMMUs. > See my proposal [1] > > 1: https://lore.kernel.org/linux-csky/1568896556-28769-1-git-send-email-guoren@xxxxxxxxxx/T/#u > -- > Best Regards > Guo Ren > > ML: https://lore.kernel.org/linux-csky/ _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
