Hi, On 13/09/2019 09:13, Guo Ren wrote: > Another idea is seperate remote TLB invalidate into two instructions: > > - sfence.vma.b.asyc > - sfence.vma.b.barrier // wait all async TLB invalidate operations > finished for all harts. It's not clear to me how this helps, but I probably don't have the whole picture. If you have a place where it is safe to wait for the barrier to complete, why not do the whole invalidate there? > (I remember who mentioned me separate them into two instructions after > session. Anup? Is the idea right ?) > > Actually, I never consider asyc TLB invalidate before, because current our > light iommu did not need it. > > Thx all people attend the session :) Let's continue the talk. > > > Guo Ren <guoren@xxxxxxxxxx <mailto:guoren@xxxxxxxxxx>> 于 2019年9月12日周 > 四 22:59写道： > > Thx Will for reply. > > On Thu, Sep 12, 2019 at 3:03 PM Will Deacon <will@xxxxxxxxxx > <mailto:will@xxxxxxxxxx>> wrote: > > > > On Sun, Sep 08, 2019 at 07:52:55AM +0800, Guo Ren wrote: > > > On Mon, Jun 24, 2019 at 6:40 PM Will Deacon <will@xxxxxxxxxx > <mailto:will@xxxxxxxxxx>> wrote: > > > > > I'll keep my system use the same ASID for SMP + IOMMU :P > > > > > > > > You will want a separate allocator for that: > > > > > > > > > https://lkml.kernel.org/r/20190610184714.6786-2-jean-philippe.brucker@xxxxxxx > > > > > > Yes, it is hard to maintain ASID between IOMMU and CPUMMU or different > > > system, because it's difficult to synchronize the IO_ASID when the CPU > > > ASID is rollover. > > > But we could still use hardware broadcast TLB invalidation instruction > > > to uniformly manage the ASID and IO_ASID, or OTHER_ASID in our IOMMU. > > > > That's probably a bad idea, because you'll likely stall execution on the > > CPU until the IOTLB has completed invalidation. In the case of ATS, > I think > > an endpoint ATC is permitted to take over a minute to respond. In > reality, I > > suspect the worst you'll ever see would be in the msec range, but that's > > still an unacceptable period of time to hold a CPU. > Just as I've said in the session that IOTLB invalidate delay is > another topic, My main proposal is to introduce stage1.pgd and > stage2.pgd as address space identifiers between different TLB systems > based on vmid, asid. My last part of sildes will show you how to > translate stage1/2.pgd to as/vmid in PCI ATS system and the method > could work with SMMU-v3 and intel Vt-d. (It's regret for me there is > no time to show you the whole slides.) > > In our light IOMMU implementation, there's no IOTLB invalidate delay > problem. Becasue IOMMU is very close to CPU MMU and interconnect's > delay is the same with SMP CPUs MMU (no PCI, VM supported). > > To solve the problem, we could define a async mode in sfence.vma.b to > slove the problem and finished with per_cpu_irq/exception. The solution I had to this problem is pinning the ASID [1] used by the IOMMU, to prevent the CPU from recycling the ASID on rollover. This way the CPU doesn't have to wait for IOMMU invalidations to complete, when scheduling a task that might not even have anything to do with the IOMMU. In the Arm SMMU, ASID and IOASID (PASID) are separate identifiers. IOASID indexes an entry in the context descriptor table, which contains the ASID. So with unpinned shared ASID you don't need to invalidate the ATC on rollover, since the IOASID doesn't change, but you do need to modify the context descriptor and invalidate cached versions of it. Once you have pinned ASIDs, you could also declare that IOASID = ASID. I don't remember finding an argument to strictly forbid it, even though ASID and IOASID have different sizes on Arm (respectively 8/16 and 20 bits). Thanks, Jean [1] https://lore.kernel.org/linux-iommu/20180511190641.23008-17-jean-philippe.brucker@xxxxxxx/ _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
