On Fri, 07 Jun 2019 04:47:29 +0100, "Saidi, Ali" <alisaidi@xxxxxxxxxx> wrote: > > > On 6/6/19, 11:55 AM, "Marc Zyngier" <marc.zyngier@xxxxxxx> wrote: > > Add the basic data structure that expresses an MSI to LPI > translation as well as the allocation/release hooks. > > THe size of the cache is arbitrarily defined as 4*nr_vcpus. > > A cache size of 8/vCPU should result in cache hits in most cases and > 16/vCPU will pretty much always result in a cache hit. What is this interesting observation based on? On the face of it, this is just as random as what I have already. Thanks, M. -- Jazz is not dead, it just smells funny. _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
