On 15 May 2015 at 17:16, Alex Bennée <alex.bennee@xxxxxxxxxx> wrote: > Mark Rutland <mark.rutland@xxxxxxx> writes: >> This gets more fun when you consider the context-aware breakpoints are >> the highest numbered. So the set of (context-aware) breakpoints might >> not intersect across all CPUs. > > I didn't see a reference to that in the ARM ARM. It seemed to imply any > breakpoint could be context aware is .BT was appropriately set and > linked to the VR. No; see D2.9.2; there must be at least one context-aware breakpoint, but no requirement for more than that. -- PMM _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
