On Thu, May 14, 2015 at 01:38:11PM +0100, Peter Maydell wrote: > On 14 May 2015 at 13:28, Paolo Bonzini <pbonzini@xxxxxxxxxx> wrote: > > Well, PCI BARs are generally MMIO resources, and hence should not be cached. > > > > As an optimization, OS drivers can mark them as cacheable or > > write-combining or something like that, but in general it's a safe > > default to leave them uncached---one would think. > > Isn't this handled by the OS mapping them in the 'prefetchable' > MMIO window rather than the 'non-prefetchable' one? (QEMU's > generic-PCIe device doesn't yet support the prefetchable window.) I was thinking (with my limited PCI knowledge) the same thing, and was planning on experimenting with that. drew _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
