On Thu, May 14, 2015 at 01:09:34PM +0200, Laszlo Ersek wrote: > On 05/14/15 12:30, Christoffer Dall wrote: > > On Wed, May 13, 2015 at 01:31:51PM +0200, Andrew Jones wrote: > >> Introduce a new memory region flag, KVM_MEM_UNCACHED, which is > >> needed by ARM. This flag informs KVM that the given memory region > >> is typically mapped by the guest as non-cacheable. KVM for ARM > >> then ensures that that memory is indeed mapped non-cacheable by > >> the guest, and also remaps that region as non-cacheable for > >> userspace, allowing them both to maintain a coherent view. > >> > >> Changes since v1: > >> 1) don't pin pages [Paolo] > >> 2) ensure the guest maps the memory non-cacheable [me] > >> 3) clean up memslot flag documentation [Christoffer] > >> changes 1 and 2 effectively redesigned/rewrote v1. Find v1 here > >> http://www.spinics.net/lists/kvm-arm/msg14022.html > >> > >> The QEMU series for v1 hasn't really changed. Only the linux > >> header hack needed to bump KVM_CAP_UNCACHED_MEM from 107 to > >> 116. Find the series here > >> http://www.spinics.net/lists/kvm-arm/msg14026.html > >> > >> Testing: > >> This series still needs lots of testing, but I thought I'd > >> kick it to the list early, as there's been recent interest > >> in solving this problem, and I'd like to get test results > >> and opinions on this approach from others sooner than later. > >> I've tested with AAVMF (UEFI for AArch64 mach-virt guests). > >> AAVMF has a kludge in it to avoid the coherency problem. > > > > How does the 'kludge' work? > > https://github.com/tianocore/edk2/commit/f9a8be42 > > (It's probably worth looking at the documentation in the first hunk too, > under the commit message.) > Why is this a hack/unintuitive? Is the semantics of the QEMU PCI bus not simply that MMIO regions are coherent? -Christoffer _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
